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Delay Test for Diagnosis of Power Switches., , , , and . IEEE Trans. VLSI Syst., 22 (2): 197-206 (2014)Efficient Variation-Aware Delay Fault Simulation Methodology for Resistive Open and Bridge Defects., , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 33 (5): 798-810 (2014)Bridge Defect Diagnosis for Multiple-Voltage Design., , , , and . European Test Symposium, page 99-104. IEEE Computer Society, (2008)High Quality Testing of Grid Style Power Gating., , , , and . ATS, page 186-191. IEEE Computer Society, (2014)Reconfigurable hardware-software codesign methodology for protein identification., , , , , , , , and . EMBC, page 2456-2459. IEEE, (2016)Efficient Static Compaction Techniques for Sequential Circuits Based on Reverse-Order Restoration and Test Relaxation., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 25 (11): 2556-2564 (2006)Co-optimization of fault tolerance, wirelength and temperature mitigation in TSV-based 3D ICs., , , and . VLSI-SoC, page 1-6. IEEE, (2016)A Framework for TSV Based 3D-IC to Analyze Aging and TSV Thermo-Mechanical Stress on Soft Errors., , and . ITC-Asia, page 121-126. IEEE, (2019)Gate-Sizing-Based Single Vdd Test for Bridge Defects in Multivoltage Designs., , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 29 (9): 1409-1421 (2010)Efficient Static Compaction Techniques for Sequential Circuits Based on Reverse Order Restoration and Test Relaxation., , and . Asian Test Symposium, page 378-385. IEEE Computer Society, (2005)