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PaRV: Parallelizing Runtime Detection and Prevention of Concurrency Errors.

, , , , and . RV, volume 7687 of Lecture Notes in Computer Science, page 42-47. Springer, (2012)

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The Velox Transactional Memory Stack., , , , , , , , , and 14 other author(s). IEEE Micro, 30 (5): 76-87 (2010)EVX: Vector execution on low power EDGE cores., , , , , , and . DATE, page 1-4. European Design and Automation Association, (2014)unreadTVar: Extending Haskell Software Transactional Memory for Performance., , , , , and . Trends in Functional Programming, volume 8 of Trends in Functional Programming, page 89-104. Intellect, (2007)A partitioned instruction queue to reduce instruction wakeup energy., , , , and . IJHPCN, 1 (4): 153-161 (2004)JSRAM: A Circuit-Level Technique for Trading-Off Robustness and Capacity in Cache Memories., , , , and . ISVLSI, page 149-154. IEEE Computer Society, (2015)Implications of non-volatile memory as primary storage for database management systems., , , , and . SAMOS, page 164-171. IEEE, (2016)Transactional Memory: An Overview., , , , , , and . IEEE Micro, 27 (3): 8-29 (2007)Runtime-Aware Architectures., , , , , , , , , and 3 other author(s). Euro-Par, volume 9233 of Lecture Notes in Computer Science, page 16-27. Springer, (2015)A Demo of FPGA Aggressive Voltage Downscaling: Power and Reliability Tradeoffs., , and . FPL, page 451-452. IEEE Computer Society, (2018)Stand-Alone Memory Controller for Graphics System., , , , , , and . ARC, volume 8405 of Lecture Notes in Computer Science, page 108-120. Springer, (2014)