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Disambiguation of "Sinaga, Saoer"

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Shellcase-Type Wafer-Level Packaging Solutions: RF Characterization and Modeling

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Other publications of authors with the same name

Modeling and Analysis of Substrate Coupling in Silicon Integrated Circuits, , and . 2002 proceedings : SAFE-ProRISC-SeSens, November 27 - 29, 2002, Veldhoven, the Netherlands, page 704-707. (2002)Processability and Electrical Characteristics of Glass Substrates for RF Wafer-Level Chip-Scale Packages, , , , , , and . 53rd Electronic Components and Technology Conference, 2003 : Proceedings., page 875-880. Piscataway, New Jersey, IEEE, (2003)On-Chip Isolation in Wafer-Level Chip-Scale Packages : Substrate Thinning And Circuit Partitioning by Trenches, , , and . Proceedings : November 18 - 20, 2003, Hynes Convention Center, Boston, MA : November 18 - 20, 2003, Hynes Convention Center, Boston, MA, Washington D.C., IMAPS, (2003)Parasitic Effects Reduction for Wafer-Level Packaging of RF-Mems, , , , , and . CoRR, (2007)RF Crosstalk Suppression Based On Wafer-Level Packaging Concept, , , and . (2006)Analysis and optimization of Via-Connected Spiral Inductors in RF Silicon Technology, , and . Proceedings 2003 : ProRISC, SAFE : November 25 - 27 2003, Veldhoven, the Netherlands, Utrecht, Technology Foundation, (2003)Influence of via-connections on electrical performance of vertically-spaced RF passives, , and . Proceedings Electronic Components and Technology, 2005. ECTC '05., 2, page 1584-1589. Piscataway, New Jersey, IEEE, (2005)Characterization of high-resistivity polycrystalline silicon substrates for wafer-level packaging and integration of RF passives, , , , , and . The Fifth International Conference on Advanced Semiconductor Devices and Microsystems, 2004. ASDAM 2004., page 227-230. Piscataway, New Jersey, IEEE, (2004)Vertical Integration of RF Passive Components in Stacked Wafer-Level Packages, , and . Conference programme & proceedings : 15th European Microelectronics and Packaging Conference & Exhibition : June 12 - 15, 2005, Brugge, Belgium, page 190-194. (2005)Wafer-Level Packaging for RF Applications Using High-Resistivity Polycrystalline Silicon Substrate Technology, , , and . Proceedings : 2004 International Symposium on Microelectronics, November 14-18, 2004, Long Beach Convention Center, Long Beach, Ca, Washington D.C., International Microelectronics and Packaging Society, (2004)