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High-Performance Complementary Bipolar Technology

J. Warnock, J. Cressler, J. Burghartz, D. Harame, K. Jenkins, and C. Chuang. Digest of technical papers : 1993 Symposium on VLSI Technology : May 17 - 19, 1993, Kyoto, page 75-76. Piscataway, New Jersey, IEEE, (1993)
DOI: 10.1109/VLSIT.1993.760244

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Dipl.-Ing. Philipp Tempel

Kinematics and dynamics modeling for real-time simulation of the cable-driven parallel robot IPAnema 3P. Tempel, P. Miermeister, and A. Pott. Proceedings of the 14th IFToMM World Congress, page 117-123. Taipei, IFToMM, (2015)

Kinematics and dynamics modeling for real-time simulation of the cable-driven parallel robot IPAnema 3P. Tempel, P. Miermeister, and A. Pott. Proceedings of the 14th IFToMM World Congress, page 117-123. Taipei, IFToMM, (2015)SimTech Status Seminar 2014 - Status Update: Improved Modeling of Cables for Kinematics and Dynamics of Light-weight RobotsP. Tempel. (Dec 12, 2014)Design and programming for cable-driven parallel robots in the German pavilion at the EXPO 2015P. Tempel, F. Schnelle, A. Pott, and P. Eberhard. Machines, 3 (3): 223-241 (2015)

Dr. rer. nat. Attila Teleki University of Stuttgart

Dr. -Ing. Kristina Terheiden University of Stuttgart

Marco Testa University of Stuttgart

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A high-performance low VMIN 55nm 512Kb disturb-free 8T SRAM with adaptive VVSS control.H. Yang, S. Yang, M. Hsia, Y. Lin, Y. Lin, C. Chen, C. Chang, G. Lin, Y. Chen, C. Chuang and 9 other author(s). SoCC, page 197-200. IEEE, (2011)SOI Digital Circuits: Design Issues.R. Puri, and C. Chuang. VLSI Design, page 474-479. IEEE Computer Society, (2000)All digitally controlled linear voltage regulator with PMOS strength self-calibration for ripple reduction.Y. Kuo, P. Huang, C. Wu, Y. Liang, C. Chuang, Y. Chu, and W. Hwang. VLSI-DAT, page 1-4. IEEE, (2015)40 nm Bit-Interleaving 12T Subthreshold SRAM With Data-Aware Write-Assist.Y. Chiu, Y. Hu, M. Tu, J. Zhao, Y. Chu, S. Jou, and C. Chuang. IEEE Trans. on Circuits and Systems, 61-I (9): 2578-2585 (2014)Single-Ended Subthreshold SRAM With Asymmetrical Write/Read-Assist.M. Tu, J. Lin, M. Tsai, S. Jou, and C. Chuang. IEEE Trans. on Circuits and Systems, 57-I (12): 3039-3047 (2010)On-Chip Process Variation Detection and Compensation Using Delay and Slew-Rate Monitoring Circuits.A. Ghosh, R. Rao, C. Chuang, and R. Brown. ISQED, page 815-820. IEEE Computer Society, (2008)Reducing parasitic BJT effects in partially depleted SOI digital logic circuits.K. Das, C. Chuang, and R. Brown. Microelectronics Journal, 39 (2): 275-285 (2008)Testing strategies for a 9T sub-threshold SRAM.H. Yang, C. Lin, H. Chen, M. Chao, M. Tu, S. Jou, and C. Chuang. ITC, page 1-10. IEEE Computer Society, (2012)Ultrahigh-Density 256-Channel Neural Sensing Microsystem Using TSV-Embedded Neural Probes.Y. Huang, P. Huang, S. Wu, Y. Hu, Y. You, M. Chen, Y. Huang, H. Chang, Y. Lin, J. Duann and 5 other author(s). IEEE Trans. Biomed. Circuits and Systems, 11 (5): 1013-1025 (2017)A 0.35 V, 375 kHz, 5.43 µW, 40 nm, 128 kb, symmetrical 10T subthreshold SRAM with tri-state bit-line.S. Wu, C. Lu, M. Tu, H. Huang, K. Lee, Y. Kao, and C. Chuang. Microelectronics Journal, (2016)