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A 45nm 4Gb 3-Dimensional Double-Stacked Multi-Level NAND Flash Memory with Shared Bitline Structure., , , , , , , , , and 3 other author(s). ISSCC, page 510-511. IEEE, (2008)A 31 ns Random Cycle VCAT-Based 4F 2 DRAM With Manufacturability and Enhanced Cell Efficiency., , , , , , , , , and 11 other author(s). J. Solid-State Circuits, 45 (4): 880-888 (2010)A Zeroing Cell-to-Cell Interference Page Architecture With Temporary LSB Storing and Parallel MSB Program Scheme for MLC NAND Flash Memories., , , , , , , and . J. Solid-State Circuits, 43 (4): 919-928 (2008)What is Needed the Most in MT-Supported Paper Writing., , and . PACLIC, page 418-427. De La Salle University (DLSU), Manila, Philippines, (2008)8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology., , , , , , , , , and 11 other author(s). J. Solid-State Circuits, 45 (1): 111-119 (2010)Design Techniques of Delay-Locked Loop for Jitter Minimization in DRAM Applications., , , and . IEICE Transactions, 88-C (4): 753-759 (2005)Resolution Improvement of Infrared Images Using Visible Image Information., , , and . IEEE Signal Process. Lett., 18 (10): 611-614 (2011)Robust learning-based super-resolution., , , , and . ICIP, page 2017-2020. IEEE, (2010)An 8 Gb/s/pin 9.6 ns Row-Cycle 288 Mb Deca-Data Rate SDRAM With an I/O Error Detection Scheme., , , , , , , , , and 1 other author(s). J. Solid-State Circuits, 42 (1): 193-200 (2007)DeepHiR: improving high-radix router throughput with deep hybrid memory buffer microarchitecture., , , , and . ICS, page 403-413. ACM, (2019)