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Disambiguation of "Kajihara, Seiji"

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Timing-Accurate Estimation of IR-Drop Impact on Logic- and Clock-Paths During At-Speed Scan Test

, , , , , , and . 2016 IEEE 25th Asian Test Symposium (ATS), page 19-24. Piscataway, IEEE, (2016)
DOI: 10.1109/ATS.2016.49

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Other publications of authors with the same name

Stuck-open faults test generation for cmos combinational circuits., , and . Systems and Computers in Japan, 22 (9): 33-42 (1991)On Test Data Volume Reduction for Multiple Scan Chain Designs., , , and . VTS, page 103-110. IEEE Computer Society, (2002)Enhanced untestable path analysis using edge graphs., , , and . Asian Test Symposium, page 139-144. IEEE Computer Society, (2000)An On-Chip Digital Environment Monitor for Field Test., , , and . ATS, page 254-257. IEEE Computer Society, (2014)CAT: A Critical-Area-Targeted Test Set Modification Scheme for Reducing Launch Switching Activity in At-Speed Scan Testing., , , , , , , and . Asian Test Symposium, page 99-104. IEEE Computer Society, (2009)Synthesis for Testability by Sequential Redundancy Removal Using Retiming., , and . FTCS, page 33-40. IEEE Computer Society, (1995)On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST., , , , , , and . Asian Test Symposium, page 19-24. IEEE Computer Society, (2013)Effective Launch-to-Capture Power Reduction for LOS Scheme with Adjacent-Probability-Based X-Filling., , , , , , , , , and 1 other author(s). Asian Test Symposium, page 90-95. IEEE Computer Society, (2011)Good Die Prediction Modelling from Limited Test Items., , , and . ITC-Asia, page 115-120. IEEE, (2018)Effective IR-drop reduction in at-speed scan testing using Distribution-Controlling X-Identification., , , , , , , , and . ICCAD, page 52-58. IEEE Computer Society, (2008)