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         "pages": "1-4","abstract": "Clock jitter sensitivity is a well-known drawback of continuous-time ΣΔ modulators. Although there exist various methods to alleviate the jitter influence, most are only effective in reducing noise incurred by out-of-band quantization noise. However, due to the steadily increasing signal frequency in receiver applications, the dominant jitter influence rather originates from the mixing between the close to in-band interferers and the close-in clock phase noise, either in a mixer or in the DAC of a bandpass ΣΔ modulator. This mixing results in additional in-band noise which cannot be reduced by existing solutions. In this paper, we use a reconfigurable digital filtering method for close to in-band interferer suppression in bandpass ΣΔ modulators, and demonstrate its effectiveness in improving phase noise tolerance through simulation. Additionally, a technique to simplify the implementation of the digital filters is proposed.",
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         "pages": "1-4","abstract": "Clock jitter sensitivity is a well-known drawback of continuous-time ΣΔ modulators. Although there exist various methods to alleviate the jitter influence, most are only effective in reducing noise incurred by out-of-band quantization noise. However, due to the steadily increasing signal frequency in receiver applications, the dominant jitter influence rather originates from the mixing between the close to in-band interferers and the close-in clock phase noise, either in a mixer or in the DAC of a bandpass ΣΔ modulator. This mixing results in additional in-band noise which cannot be reduced by existing solutions. In this paper, we use a reconfigurable digital filtering method for close to in-band interferer suppression in bandpass ΣΔ modulators, and demonstrate its effectiveness in improving phase noise tolerance through simulation. Additionally, a technique to simplify the implementation of the digital filters is proposed.",
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