The rising complexity of integrated devices has led to new defect types and failure modes at the system level that are not detected by structural tests. System-Level Test (SLT) is another test step to combat this challenge. SLT is in charge of exercising system-level interactions between hardware components and software. Non-functional properties, e.g., temperature, play a major role in SLT.This work focuses on the automatic generation of assembly test programs for SLT that aim to indirectly maximize a particular non-functional property, for example, the temperature. It is based on two-step generation with genetic algorithms. First, a fast architectural simulation is used with the genetic algorithm to provide a structure for the test programs. Afterward, an additional generation is done on the hardware to optimize the initial register contents of the program.The case study for gathering experimental results is a super-scalar out-of-order RISC-V processor, the Berkeley Out-of-Order Machine (BOOM). Experimental results show that the two-step generation is more effective in converging to a better power-hungry test program than only using the power consumption as a fitness function for the genetic algorithm.
%0 Conference Paper
%1 schwachhofer2024optimizing
%A Schwachhofer, Denis
%A Angione, Francesco
%A Becker, Steffen
%A Wagner, Stefan
%A Sauer, Matthias
%A Bernardi, Paolo
%A Polian, Ilia
%B 2024 IEEE European Test Symposium (ETS)
%D 2024
%K RISC-V System-LevelTest genetiProgramming geneticAlgorithms stressTest testGeneration
%P 1-4
%R 10.1109/ETS61313.2024.10567817
%T Optimizing System-Level Test Program Generation via Genetic Programming
%U http://dx.doi.org/10.1109/ets61313.2024.10567817
%X The rising complexity of integrated devices has led to new defect types and failure modes at the system level that are not detected by structural tests. System-Level Test (SLT) is another test step to combat this challenge. SLT is in charge of exercising system-level interactions between hardware components and software. Non-functional properties, e.g., temperature, play a major role in SLT.This work focuses on the automatic generation of assembly test programs for SLT that aim to indirectly maximize a particular non-functional property, for example, the temperature. It is based on two-step generation with genetic algorithms. First, a fast architectural simulation is used with the genetic algorithm to provide a structure for the test programs. Afterward, an additional generation is done on the hardware to optimize the initial register contents of the program.The case study for gathering experimental results is a super-scalar out-of-order RISC-V processor, the Berkeley Out-of-Order Machine (BOOM). Experimental results show that the two-step generation is more effective in converging to a better power-hungry test program than only using the power consumption as a fitness function for the genetic algorithm.
@inproceedings{schwachhofer2024optimizing,
abstract = {The rising complexity of integrated devices has led to new defect types and failure modes at the system level that are not detected by structural tests. System-Level Test (SLT) is another test step to combat this challenge. SLT is in charge of exercising system-level interactions between hardware components and software. Non-functional properties, e.g., temperature, play a major role in SLT.This work focuses on the automatic generation of assembly test programs for SLT that aim to indirectly maximize a particular non-functional property, for example, the temperature. It is based on two-step generation with genetic algorithms. First, a fast architectural simulation is used with the genetic algorithm to provide a structure for the test programs. Afterward, an additional generation is done on the hardware to optimize the initial register contents of the program.The case study for gathering experimental results is a super-scalar out-of-order RISC-V processor, the Berkeley Out-of-Order Machine (BOOM). Experimental results show that the two-step generation is more effective in converging to a better power-hungry test program than only using the power consumption as a fitness function for the genetic algorithm.},
added-at = {2024-09-12T16:38:36.000+0200},
author = {Schwachhofer, Denis and Angione, Francesco and Becker, Steffen and Wagner, Stefan and Sauer, Matthias and Bernardi, Paolo and Polian, Ilia},
biburl = {https://puma.ub.uni-stuttgart.de/bibtex/261465ac6403a9ff199b6ee85f7d3dfcf/dschwachhofer},
booktitle = {2024 IEEE European Test Symposium (ETS)},
doi = {10.1109/ETS61313.2024.10567817},
interhash = {83f82058736c95d624b41163fc208d75},
intrahash = {61465ac6403a9ff199b6ee85f7d3dfcf},
issn = {1558-1780},
keywords = {RISC-V System-LevelTest genetiProgramming geneticAlgorithms stressTest testGeneration},
month = may,
pages = {1-4},
timestamp = {2024-09-12T16:38:36.000+0200},
title = {Optimizing System-Level Test Program Generation via Genetic Programming},
url = {http://dx.doi.org/10.1109/ets61313.2024.10567817},
year = 2024
}