Inproceedings

System Platform Requirements for High Performance CNCs

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Proceeding of the 22nd International Conference on Flexible Automation and Intelligent Manufacturing FAIM 2012, page pp. 837-844. Tampere, Tampere University of Technology, (2012)

Abstract

Todays computer numerical control (CNC) systems controlling machine toolshave to meet high requirements: Short control sampling periods shall increaseinterpolation accuracy and productivity while the path trajectory planning andinterpolation algorithms are getting more complex at the same time. CNCsystems therefore have to be built upon powerful system platforms.Even though control systems already have highly developed processing units attheir disposal, this paper illustrates the further need for high-performancesystem platforms as they are already available in the IT. By identifyingdifferent processing scenarios this paper demonstrates how actual CNC systemscan be driven into its limitation regarding processing power. Each scenario iscausing different loads in the CNC kernel. In the area of high speed cutting(HSC) the look ahead is charged heavily whereas multi-axes processing andcomplex path interpolation algorithms like splines causing bigger loads in theinterpolation module.From this observation the paper derives requirements for a suitable systemplatform to cope with the increased needs for processing power in the area ofCNC systems. As with single-core CPUs performance reached a physical limit,only parallel system platforms can provide sufficient processing power. Withmulticore CPUs more than sufficient performance is provided. Hence, first CNCsystems supporting asymmetric multiprocessing have emerged. By separatingrealtime and non-realtime operating system and by allocating CNC modules todedicated cores of the processing unit, each module has the full processingpower of one CPU-kernel. Symmetric multiprocessing (SMP), however, couldcontribute even more to build a high-performance industrial control system,despite the need of modifications in the software architecture to allowparallel code execution.

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