Autonomic Thread Parallelism and Mapping Control for Software Transactional Memory. (Contrôle Autonomique du Parallélisme et du Placement de Threads pour les Mémoires Transactionnelles Logicielles).
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%0 Thesis
%1 phd/hal/Zhou16
%A Zhou, Naweiluo
%D 2016
%K dblp
%T Autonomic Thread Parallelism and Mapping Control for Software Transactional Memory. (Contrôle Autonomique du Parallélisme et du Placement de Threads pour les Mémoires Transactionnelles Logicielles).
@phdthesis{phd/hal/Zhou16,
added-at = {2017-01-09T00:00:00.000+0100},
author = {Zhou, Naweiluo},
biburl = {https://puma.ub.uni-stuttgart.de/bibtex/234be45400d1de842d153bf27ddd81e91/dblp},
ee = {https://tel.archives-ouvertes.fr/tel-01408450},
interhash = {00f34e9d5d3a877d6305872ebb928163},
intrahash = {34be45400d1de842d153bf27ddd81e91},
keywords = {dblp},
school = {INRIA, France},
timestamp = {2017-01-10T10:36:03.000+0100},
title = {Autonomic Thread Parallelism and Mapping Control for Software Transactional Memory. (Contrôle Autonomique du Parallélisme et du Placement de Threads pour les Mémoires Transactionnelles Logicielles).},
year = 2016
}
